Memory structure to minimize rounding/trunction errors for n-dim

Details Memory structure to minimize rounding/trunction errors for n-dim Memory structure to minimize rounding/trunction errors for n-dim

1994-05-09

1995-06-27

Nguyen, Viet Q.

Static information storage and retrieval

Plural shift register memory devices

364725, 364745, 364726, 382232, 382276, G06F 15332, G06F 738

Patent

active

054285674

ABSTRACT:
A method for computing n-dimensional decomposable image transformation using the 1D approach with constrained transpose memory provides a minimized rounding/truncation error. The method minimizes transpose memory size required to fulfill a defined accuracy requirement for n-dimensional image transformation. A set of input data elements are stored. Then, a first transform, of the multiple dimension transform, is performed on the set of input data elements so as to form an array of transformed data elements, each of the transformed data elements having a larger number of bits than the input data elements. A common range of the transformed data elements is determined, and a minimum number of bits required to represent the common range without loss of information is then determined. The memory word size available for storage of the transformed data elements is compared with a minimum number of bits so as to determine an excess number of bits. Only the excess number of bits of the transformed data is truncated/rounded so as to form an output set of data elements. Finally, the output set of data elements is stored.

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patent: 4829465 (1989-05-01), Knauer et al.
patent: 5177704 (1993-01-01), D'Luna
patent: 5218563 (1993-06-01), Juri et al.

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