Memory structure for nonsequential storage of block bytes in mul

Details Memory structure for nonsequential storage of block bytes in mul Memory structure for nonsequential storage of block bytes in mul

1985-10-28

1989-01-03

Zache, Raulfe B.

Boots, shoes, and leggings

365230, 371 37, 371 39, 371 40, G06F 1202, G06F 1204

Patent

active

047962224

ABSTRACT:
A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a common high order address bus and different low order address bus. The low order addresses are generated such that an ordered sequence of bits, beginning at the starting address, is transferred in parallel to the register from both chips, regardless of the starting address.

REFERENCES:
patent: 2653996 (1953-09-01), Wright
patent: 3064080 (1962-11-01), Rea et al.
patent: 3331061 (1967-07-01), Marcus
patent: 3685020 (1972-08-01), Meade
patent: 3895360 (1975-07-01), Crichi et al.
patent: 4442503 (1984-04-01), Schutt et al.
patent: 4580214 (1986-04-01), Kubo et al.
patent: 4667308 (1987-05-01), Hayes et al.

Affiliated with

Also associated with

Rating

Memory structure for nonsequential storage of block bytes in mul does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory structure for nonsequential storage of block bytes in mul, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory structure for nonsequential storage of block bytes in mul will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2173122