Memory structure for nonsequential storage of block bytes in mul

Details Memory structure for nonsequential storage of block bytes in mul Memory structure for nonsequential storage of block bytes in mul

1988-08-12

1991-02-12

Williams, Jr., Archie E.

Boots, shoes, and leggings

3649611, 364933, 3649583, 364252, 3642549, 364260, 364247, 3642463, 3642521, 3649591, 3649664, G06F 93, G06F 1316, G06F 1204, G06F 1206

Patent

active

049929798

ABSTRACT:
A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a common high order address bus and different low order address bus. The low order addresses are generated such that an ordered sequence of bits, beginning at the starting address, is transferred in parallel to the register from both chips, regardless of the starting address.

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