Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-01-11
2011-01-11
Sofocleous, Alexander (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C326S039000, C365S154000, C365S189080, C365S189200
Reexamination Certificate
active
07869275
ABSTRACT:
An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile. Each memory structure of a register includes a non-volatile floating gate cell (that stores the configuration information) as well as a volatile cell. All transistors have the same gate insulator thickness. Although a programming pulse signal is applied to all memory structures, the state of the non-volatile cell of a memory structure is only changed if the state stored by the associated non-volatile cell differs from the state stored by the volatile cell. Floating gates are automatically refreshed by the programming pulse signal. By storing configuration information in each tile, inefficiencies associated with using blocks of non-volatile memory are avoided.
REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 5311470 (1994-05-01), Atsumi et al.
patent: 5428568 (1995-06-01), Kobaryashi et al.
patent: 5428571 (1995-06-01), Atsumi et al.
patent: 5592415 (1997-01-01), Kato et al.
patent: 5682345 (1997-10-01), Roohparvar et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6252823 (2001-06-01), McDonald et al.
patent: 6362675 (2002-03-01), Alwais
patent: 6401163 (2002-06-01), Kondo et al.
patent: 6507943 (2003-01-01), Kelem
patent: 6639839 (2003-10-01), Chou et al.
patent: 7053652 (2006-05-01), de Jong
patent: 7135886 (2006-11-01), Schlacter
patent: 7474559 (2009-01-01), Lakkapragada et al.
patent: 7581198 (2009-08-01), Huynh et al.
patent: 2003/0124791 (2003-07-01), Summerfelt et al.
patent: 2003/0214321 (2003-11-01), Swami et al.
patent: 2006/0080631 (2006-04-01), Koo
patent: 2006/0123376 (2006-06-01), Vogel et al.
patent: 08306192 (1996-11-01), None
English Abstract for JP 08306192 A. Nov. 1996.
International Search Report and Written Opinion of International Searching Authority for PCT/US07/21379 dated Mar. 10, 2008 (13 pages).
Yamauchi et al., “A Versatile Stacked Storage Capacitor on FLOTOX Cell for Megabit NVRAMs”, IEEE Trans. on Electron Devices, vol. 39, No. 12, pp. 2791- 2796 (Dec. 1992).
Ohsaki et al., “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid-State Circuits, vol. 29, No. 3, pp. 311- 316 (Mar. 1994).
Simon J. Lovett, “The Nonvolatile Cell Hidden in Standard CMOS Logic Technologies”, IEEE Trans. on Electron Devices, vol. 48, No. 5, pp. 1017-1018 (May 2001).
Grant Matthew A.
Huynh Steven
Kunst David J.
Active-Semi, Inc.
Imperium Patent Works
Sofocleous Alexander
Wallace Darien K.
LandOfFree
Memory structure capable of bit-wise write or overwrite does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory structure capable of bit-wise write or overwrite, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory structure capable of bit-wise write or overwrite will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2651735