Static information storage and retrieval – Addressing – Counting
Reexamination Certificate
2001-04-30
2003-05-20
Nelms, David (Department: 2824)
Static information storage and retrieval
Addressing
Counting
C365S231000
Reexamination Certificate
active
06567340
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of digital integrated circuits and, in particular, to counters.
BACKGROUND OF THE INVENTION
A counter is a digital circuit that can count in discrete increments based on data input to the counter. A counter may be constructed from an array of flip-flops in which the flip-flops are interconnected in such a manner that the array advances from state to state with each cycle of a input waveform, such as a clock signal. A counter starts from some initial state, advances through other possible states, and then may return to the initial state. Counters may be designed using different types of flip-flops.
A flip-flop, in essence, is a logic circuit that has a memory. That is, given the present logic levels at its inputs, it is possible from an examination of the output to determine what the logic levels were at the inputs immediately before they attained the present levels. A clocked flip-flop is one that can change state only when a clock input signal transitions states, no matter how many changes occur at the inputs. As such, the output is held constant while some of the inputs may be changing.
FIG. 1A
illustrates a particular type of counter, known as a ripple counter. The ripple counter is designed with a particular type of clocked flip-flop, known as a D-type flip-flop. D, or data, flip-flops have only a single data input (as opposed to two inputs as with other types of flip-flops) and a clock input. Regardless of the input level, the D input is transferred to the output with the next state of the output given by the current value of the input. D flip-flops use combinational logic circuits (e.g., NAND gates, NOR gates) to perform this function. By connecting D flip-flops in the illustrated manner, a ripple counter may be formed.
The ripple counter has outputs of a preceding flip-flop fed to the clock input of a subsequent flip-flop in the chain. In this manner, each flip-flop changes state only when a preceding flip-flop changes logic states. The flip-flops toggle on the positive transitions (low-to-high) of the waveform at the clock input. The ripple counter generates a 3-bit (b
0
, b
1
, b
2
) binary count on the outputs (Q) of the flip-flops that cycles from 000 through 111 and back to 000. The ripple counter is asynchronous, since counts occur in a subsequent flip-flop only after data output from a preceding flip-flop has a positive state transition. This is in contrast to a synchronous counter where the clock input feeds into all three flip-flop simultaneous so that the outputs of all the flops change at the same time.
The ripple counter of
FIG. 1A
is an up-counter that counts in a direction of increasing binary numbers. Other types of counters include down-counters that counts in a direction of decreasing binary numbers and up-down counters that either add to, ignore, or subtract from the current count at any time.
The D flip-flops of the ripple counter of
FIG. 1A
may be designed with latches configured in a master-slave relationship, as illustrated in
FIG. 1B. A
latch is a form of flip-flop that has the ability to remember a previous input and store it until the latch is overwritten or cleared. Two individually clocked latches, a master and a slave, may be used. The clock (CLK) signal is applied to the master latch, but the clock complement ({overscore (CLK)}) is applied to the slave latch. The slave latch provides the output signal and the master latch provides storage for the input data. Because of this storage, input data is available to the slave when the clock is at the level at which the input is disabled. The D flip-flop may also be designed with set and reset functions, as illustrated in FIG.
1
C.
One problem with prior flip-flops that use conventional logic circuitry for data storage such as formed by the cross-coupled NOR gates of
FIG. 1C
is that the NOR gates are typically unbalanced to allow for setting and resetting of the storage nodes. Such unbalancing may undesirably increase the size of the flip-flop and, thereby, the size of ripple counters formed with such flip-flops. Another disadvantage of the flip-flop of
FIG. 1C
is that it is typically fabricated using CMOS transmission gates. This also may undesirably increase the size of the flip-flop and the size of a ripple counter formed with such flip-flops.
The ripple counters of
FIG. 1A
may be combined together to form an array of counters.
FIG. 2
illustrates a conventional structure for a counter array. For example, a counter array may have N counters with each counter having k output bit lines. An additional k-bit counter may be coupled to the inputs of the N counters to pre-load the counters. In order to select among the outputs of the N counters in the array, an N, k-bit to 1, k-bit multiplexer may be coupled to the array. A multitude of select signals may be generated, for example, by circuitry that enables one of the counter outputs to be output from the multiplexer. One problem with the array structure illustrated in
FIG. 2
is that it requires significant area for the circuitry and routing necessary to access each counter's count to perform load, reset, increment, and decrement functions.
SUMMARY OF THE INVENTION
The present invention pertains to an array of counters having memory cells. In one embodiment, the apparatus includes a counter array having a plurality of counters, each counter having a memory cell. The apparatus may also include an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/write circuitry coupled to the counter array to pass data with the counter array.
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Khanna Sandeep
Nataraj Bindiganavale S.
Srinivasan Varadarajan
Blakely , Sokoloff, Taylor & Zafman LLP
Nelms David
Netlogic Microsystems Inc.
Nguyen Thinh
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