Memory selftest method and apparatus same

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271 27, 364717, G06F 1100

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050330489

ABSTRACT:
A method and apparatus for testing each memory location of a memory device, the method comprising the steps of: generating each of the memory addresses corresponding to each memory location in a pseudo-random order; generating a pseudo-random series of data words; storing one of the data words at each memory location; reading each data word back from memory; regenerating the series of data words; and comparing each read data word to the corresponding regenerated data word. The invention features generating and storing a second series of data words, each data word being inverse of the data words in the first series. The second series of data words are read from memory and compared to regenerated data. The invention also features a novel linear feedback shift register for generating the pseudo-random memory addresses and can generate the address zero. An accumulating register is utilized to store the approximate location of malfunctioning memory locations.

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patent: 4713605 (1987-12-01), Iyer
patent: 4715034 (1987-12-01), Jacobson
patent: 4780627 (1988-10-01), Illman
patent: 4782487 (1988-11-01), Smelser
Daehn, "A Test Generator IC for Testing Large CMOS-RAMs" (Sep. 1986) IEEE, pp. 18-24.
Sun et al., "Self-Testing of Embedded RAMs", (Oct. 1984) IEEE, pp. 148-156.
IBM Technical Disclosure Bulletin, (Aug. 1982) pp. 1216-1227.

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