Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1992-02-03
1994-04-05
Dixon, Joseph L.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518911, 365204, 3652256, G11C 700, G11C 800
Patent
active
053011635
ABSTRACT:
A selection circuit for a bipolar ECL memory having memory cell connected to cell selection lines and, more particularly, to upper and lower wordlines. The circuit includes a line driver connected to the upper wordline, an input stage for controlling the line driver to activate the upper wordline connected thereto in response to an address signal, and a switching device responsive to the input stage for applying a discharging current to the lower word line to speed up deactivation of the memory cell in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.
REFERENCES:
patent: 4348747 (1982-10-01), Takahashi
patent: 4357687 (1982-11-01), Rufford
patent: 4370736 (1983-01-01), Takahashi
patent: 4394657 (1983-07-01), Isogai et al.
patent: 4477885 (1984-10-01), Sharp
patent: 4500799 (1985-02-01), Sud et al.
patent: 4520462 (1985-05-01), Yamada et al.
patent: 4578779 (1986-03-01), Chan et al.
patent: 4611303 (1986-09-01), Kitano
patent: 4618944 (1986-10-01), Okajima
patent: 4692638 (1987-09-01), Stiegler
patent: 4706222 (1987-11-01), Kwiatkowski et al.
patent: 4798977 (1989-01-01), Sakui et al.
patent: 4821234 (1989-04-01), Nakasa
patent: 4891793 (1990-01-01), Anumi
Varadarajun, H. "Decoder for Ground-Up Array with STL-Compatible Output" IBM Technical Disclosure Bulletin vol. 20 No. 4 Sep. 1977.
Bordon, G. et al. "Top-Line Selection Circuit in a Memory Cell" IBM Technical Disclosure Bulletin vol. 20 No. 8 Jan. 1978.
IBM Technical Disclosure Bulletin, vol. 32, No. 2, Jul. 1989, pp. 272-274.
Homma et al., "A 35 ns, 2-W, 20-mm, 16-kbit ECL Bipolar RAM", IEEE Journal of Solid State Circuits, vol. SC-21, No. 5, Oct. 1986 pp. 675-680.
Reinschmidt Robert M.
Sullivan Steven C.
Digital Equipment Corp.
Dixon Joseph L.
Lane Jack A.
Maloney Denis G.
Paciulan Richard J.
LandOfFree
Memory selection/deselection circuitry having a wordline dischar does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory selection/deselection circuitry having a wordline dischar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory selection/deselection circuitry having a wordline dischar will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-517415