Memory security circuit using the simultaneous occurance of two

Details Memory security circuit using the simultaneous occurance of two Memory security circuit using the simultaneous occurance of two

1980-07-28

1983-05-17

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

043843263

ABSTRACT:
A control circuit to disable the operation of a semiconductor microprocessor memory device in event of an unauthorized attempt to access the memory. The memory device is disabled from operation upon removal of the device from the microprocessor. A delayed signal generated outside the memory device enables the control circuit to generate a memory enabling signal. Logic circuit means including a counter generates a signal for a preselected time period during which the delayed signal is required to be generated. Both signals control the enabling of the memory device.

REFERENCES:
patent: 3736569 (1973-05-01), Bouricius et al.
patent: 4089052 (1978-05-01), Gruner

Affiliated with

Also associated with

Rating

Memory security circuit using the simultaneous occurance of two does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory security circuit using the simultaneous occurance of two , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory security circuit using the simultaneous occurance of two will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1569506