Memory row line driver circuit

Details Memory row line driver circuit Memory row line driver circuit

2001-09-28

2002-11-26

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185230

Reexamination Certificate

active

06487139

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present disclosure relates to circuitry for writing data into nonvolatile memories, and in particular to providing high voltage pulses with variable base voltage levels.
2. The Prior Art
In typical floating gate nonvolatile memories, it is necessary to apply much higher voltages to the array when writing data into the memory than when reading data from the memory. This frequently requires that the transistors used to route the bias voltages employed to write to the memory be different than those used for reading operations. Generally, it is desirable not to consume static power in the circuits used to route the write bias voltages to reduce the write power consumption and, more importantly, to avoid excessive current draw from on chip charge pumps used to generate the high write voltages.
The prior art has labored to design suitable circuits to write nonvolatile memories. Typically, early efforts employed either charge pumps or boot-strap circuits in order to supply write biases using only n-channel transistors. With the development of technologies that would support high voltage, complimentary MOSFETs, the design problem was somewhat simplified and many products were designed using the “half-latch” circuit shown in
FIG. 1
, and disclosed in William Ip, et al, “256 kb CMOS EPROM”, ISSCC Digest of Technical Papers, pp. 138-9 (1984), and Sanjay Mehrotra et al, “A 64 kb CMOS EEPROM with On-Chip ECC”, ISSCC Digest of Technical Papers, pp. 142-3 (1984).
As manufacturing technology for integrated circuits has been scaled to finer feature sizes, the size of memory cells has been reduced, allowing more bits to be stored in a given area. However, the voltage handling capability of the transistors has also decreased. Unfortunately, the magnitude of the voltages required to write data into nonvolatile memories has not decreased as fast as the voltage handling capability of the scaled transistors.
In order to reduce the stress on the transistors in the writing circuitry, the prior art developed “split-voltage” approaches to writing in which a positive voltage was applied to one node of the cells to be written to, while another voltage of the opposing polarity was applied to another node of the cells to be written. Such an approach is disclosed in Y. Miyawaki et al, “A new Erasing and Row Decoding Scheme for Low Supply Voltage Opeation 16 Mb/64 Mb flash EEPROMs”, Symp. on VLSI Circuits Digest of Technical Papers, pp. 85-6 (1991), Shinichi Kobayashi, et al, “A 3.3 V-Only 16 Mb DINOR Flash Memory”, ISSCC Digest of Technical Papers, pp. 122-3 (1995), Masao Kuriyama, “A 5V-Only 0.6 &mgr;m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure”, ISSCC Digest of Technical Papers, pp. 152-3 (1992).
While these methods have resulted in the reduction in voltage stress across the individual transistors, two charge pumps, one for positive and one for negative voltages, are typically required. Furthermore, more complex decoder circuitry are also required that occupies a greater area.
FIG. 1
shows a simplified schematic drawing of an embodiment of typical, prior art row circuitry
100
. The NAND circuit
10
receives m addresses and their complements and is configured to operate as a decoder. The output
12
of the NAND decoder
10
of a selected row is raised to V
DD
, while the outputs of the decoders of the unselected rows is lowered to ground. An n-channel transistor
20
has a gate biased at V
DD
for allowing the signal from the NAND decoder
10
to pass to a row line
22
. Transistors
34
and
36
form an inverter.
In operation, if the output
12
of the NAND decoder
10
is low, transistor
36
is non-conducting and transistor
34
is conducting, pulling node
38
high. This will tend to turn off transistor
30
, allowing the row line
22
to be biased at ground. If the output
12
of the NAND decoder
10
is high, transistor
36
will be biased into conduction while the channel conductance of transistor
34
will be reduced so that node
38
will be pulled toward ground. As the voltage on node
38
is reduced, the conductance of transistor
30
is increased which pulls the row line up to the source potential of transistors
30
and
34
. This bias blocks conduction through transistor
34
and ultimately pulls row line
22
to the potential of node
40
.
In the read mode, the circuit simply operates as described above with node
40
equal to V
DD
. In the write mode, node
40
is biased at V
DD
until the latch consisting of transistors
30
,
34
, and
36
is set to a known state by the output of the NAND, with the inverter consisting of
34
and
36
in a non-conducting state. After the latch is set, bias on node
40
is gradually increased to a high voltage level, V
PP
. If the NAND output
12
is low, the row line
22
is actively held low by this circuit. The potential of node
38
follows that of node
40
because of the conduction through transistor
34
, which keeps transistor
30
in the non-conducting state. If the NAND output
12
is high, transistor
30
is conducting which maintains the row line at the potential of node
40
so that transistor
34
remains in a nonconducting state. In this case, the gate and source of transistor
20
are both biased at V
DD
so that this transistor is nonconducting as the row line is pulled to V
PP
. When word line
22
goes to V
PP
, transistor
20
acts as an isolation or blocking device for the low voltage NAND decoder. This allows the NAND decoder to be formed of high performance, low voltage transistors.
A disadvantage of the prior art circuit shown in
FIG. 1
is that at least one of the transistors in the latch has the full V
PP
voltage between source and drain and at least one of these transistors has V
PP
applied between gate and channel. As is appreciated by those of ordinary skill in the art, this voltage stresses the transistors of the latch.
SUMMARY OF THE INVENTION
The present disclosure provides circuitry for supplying pulses to the memory array for the purpose of writing data to the memory. The circuitry allows operation with one of the high or low level of the pulses set to an arbitrary level that is between the minimum and maximum voltage levels, thus reducing the maximum voltage handling required of the transistors of the circuitry. The disclosed circuitry provides this capability while retaining a low transistor count that allows the circuit to occupy a small area such that it can be readily interfaced to a memory array.
Various aspects of a line driver circuit are disclosed. In one aspect, the line driver circuit may comprise a first supply voltage potential node; a second supply voltage potential node; a latch node; a first transistor of a first conductivity type and having a source coupled to the first supply voltage potential node, a drain coupled to the latch node, and a gate; a second transistor of the first conductivity type and having a source coupled to the first supply voltage potential node, a drain coupled to the gate of the first transistor of the first conductivity type, and a gate coupled to the latch node; a first transistor of a second conductivity type opposite to the first conductivity type and having a drain coupled to the drain of the first transistor of the first conductivity type, a source coupled to the second supply voltage potential node and a gate coupled to the drain of the second transistor of the first conductivity type; and a diode having an anode coupled to the second supply voltage and a cathode coupled to the row line voltage potential node. The diode of the disclosed line driver circuits may include a diode connected transistor, an isolated pn diode formed in a triple-well CMOS process, or a pin diode formed in polysilicon deposited on an insulating film.


REFERENCES:
patent: 5208773 (1993-05-01), Okitaka et al.
patent: 5233206 (1993-08-01), Lee et al.
patent: 5490105 (1996-02-01), Chandna et al.
patent: 5497345 (1996-03-01), Cappelletti

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