Boots – shoes – and leggings
Patent
1985-12-17
1986-06-10
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 900
Patent
active
045946566
ABSTRACT:
A memory refresh control scheme is provided wherein the refresh timing and address signals are independent of memory configuration or the configuration of an interface unit. Since the system relates to a distributed memory arrangement, the refresh control signal and the refresh address signals are simultaneously sent to the corresponding address portions of each of the concerned memory sections and to the interface units. The logic involved in generating the refresh signal includes a first counter, driven by the system clock, which periodically generates the refresh request control signal. A second counter generates a digital address for the portion of the memory units to be refreshed. The second counter is incremented by each successive output control signal from the first counter. The digital address generated by the second counter along with the control signal generated by the first counter are simultaneously transmitted to each memory sector and to the interface unit directly associated with those memory sectors. In a distributed system there will be more than one interface unit with its associated memory sectors. Since a feature of the distributed system is the intercommunication between the component parts, it is necessary that the refresh request signal and the refresh address signals be synchronized with respect to the other units.
REFERENCES:
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4158883 (1979-06-01), Kadono et al.
patent: 4185323 (1980-01-01), Johnson et al.
patent: 4249247 (1981-02-01), Patel
patent: 4317169 (1982-02-01), Panepinto
patent: 4368466 (1983-01-01), Dwire
Dorsey Daniel K.
Medved A.
Sapelli A. A.
Shaw Gareth D.
Solakian J. S.
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