Memory redundancy addressing circuit for adjacent columns in a m

Details Memory redundancy addressing circuit for adjacent columns in a m Memory redundancy addressing circuit for adjacent columns in a m

1992-08-18

1994-01-25

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

36523009, 365236, 371 103, 307219, G06F 1116, G11C 8041

Patent

active

052818683

ABSTRACT:
A circuit for automatically addressing and activating redundant circuits on an integrated circuit chip during testing, thereby improving efficient use of the space available for fuses and fuse pads. The circuit uses an integral number of fuses, whose blown and unblown combination represents 2**n possible states. Each state represents the address of a particular circuit or set of circuits gone bad on the chip which needs to be replaced. By employing an incrementor, the logical address representing the circuit or set of circuits physically adjacent to the bad circuit is also replaced. More sophisticated incrementors may be used to address more than one adjacent circuit or sets of circuits having a non-incremental address.

REFERENCES:
patent: 4233682 (1980-11-01), Liebergot et al.
patent: 4633429 (1986-12-01), Lewandowski et al.
patent: 4800535 (1989-01-01), McAlpine
patent: 4847810 (1989-07-01), Tagami
patent: 5157628 (1992-10-01), Tani

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