Memory readback check apparatus

Details Memory readback check apparatus Memory readback check apparatus

1988-08-22

1990-11-20

Fleming, Michael R.

Excavating

371 215, 371 213, G06F 1132, G06F 1100

Patent

active

049724185

ABSTRACT:
A memory check circuit for a memory system using a plurality of memories whose write addresses and read addresses are automatically updated in response to a data write and read clock pulse, includes a selector coupled to the plurality of memories for inserting a unique word for data error detection into a data sequence at predetermined interval and for providing a unique word-inserted data sequence, and a write clock pulse supplying device for supplying the write clock pulse to each of the plurality of memories while a read clock pulse supplying device supplies the read clock pulse to each of the plurality of memories. A unique word detection device detects the unique word from data read out from the plurality of memories in response to the read clock pulse and generates a detection signal. A timer counts a predetermined period of time and generates a reset signal to reset the plurality of memories if the detection signal is not generated within the predetermined time period.

REFERENCES:
patent: 4355390 (1982-10-01), Hollwig
patent: 4661930 (1987-04-01), Tran
patent: 4726024 (1988-02-01), Guziak
patent: 4744058 (1988-05-01), Kawachima
patent: 4782486 (1988-11-01), Lipcon
patent: 4788684 (1988-11-01), Kawaguchi
patent: 4807186 (1989-02-01), Olnishi

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