Memory read circuit with precharging limitation device

Details Memory read circuit with precharging limitation device Memory read circuit with precharging limitation device

1998-04-13

1999-11-16

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 365205, G11C 1606

Patent

active

059869372

ABSTRACT:
Disclosed is a memory read circuit with a device to limit the precharging of the bit lines. The circuit includes a portion forming a current mirror and providing furthermore for a controlled precharging of the bit line and of the reference line in limiting the precharging potential to a borderline value referenced with respect to the ground. The circuit may be applied to non-volatile (EEPROM, Flash EPROM) memories, and especially memories supplied with low voltages.

REFERENCES:
patent: 5091888 (1992-02-01), Akaogi
patent: 5198997 (1993-03-01), Arakawa
patent: 5206552 (1993-04-01), Iwashita
patent: 5258959 (1993-11-01), Dallabora et al.
patent: 5353249 (1994-10-01), Itano
patent: 5675535 (1997-10-01), Jinbo

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