Memory protection system

Details Memory protection system Memory protection system

1980-01-21

1982-05-25

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 700

Patent

active

043320090

ABSTRACT:
A memory protect circuit (12) is provided for protecting inadvertent alteration of data stored in a data storage unit (32) of a data processing system (10). The data processing system (10) includes a microprocessor (14) for generating an address signal to selected storage locations of the storage unit (32) and for generating a key code prior to generation of the address signal. The write protect circuitry (12) includes decode circuitry (50) for receiving the key code and for generating a decoded key code. A latch (54) receives the decoded key code and generates a control signal upon receipt of the decoded key code. A NAND gate (62) receives the control signal and the address signal to generate an access signal for application to the storage unit (32) to permit alteration of data stored at a selected storage location of the storage unit (32) through a write operation. Latch (54) prevents generation of the control signal immediately following a write operation unit receipt by the decode circuitry (50) of a subsequently generated key code.

REFERENCES:
patent: Re27239 (1971-11-01), Ulrich
patent: 3264615 (1966-08-01), Case et al.
patent: 3328765 (1967-06-01), Amdahl et al.
patent: 3576544 (1971-04-01), Cordero et al.
patent: 4093986 (1978-06-01), Bodner et al.
patent: 4128874 (1978-12-01), Pertl et al.

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