Memory protection arrangement

Details Memory protection arrangement Memory protection arrangement

1980-12-01

1983-06-14

Richardson, Robert L.

Static information storage and retrieval

Powering

307 64, 3072383, 365228, 365229, G11C 1134

Patent

active

043887066

ABSTRACT:
A memory protection arrangement particularly suitable for use with battery backed-up CMOS RAMs. The voltage level of power to the CMOS RAMs is referenced to the logic supply to eliminate latch-up and low voltage problems and to relax the tolerances required in power supply circuits. In addition, the master chip enable for all CMOS RAMs is latched rather than providing a separate latch for individual chip enable. Furthermore, the state of the logic supply is latched at the beginning of each memory cycle to prevent disabling of the CMOS RAMs during a cycle. An additional voltage sensor controls the enable of a buffer for each chip enable.

REFERENCES:
patent: 4122359 (1978-10-01), Breikss
patent: 4145761 (1979-03-01), Gunter et al.

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