Memory presence and type detection using multiplexed memory line

Details Memory presence and type detection using multiplexed memory line Memory presence and type detection using multiplexed memory line

1996-03-28

1998-02-03

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Multiplexing

36523003, 36523001, 36523006, 36523008, G06F 1214, G11C 504

Patent

active

057152071

ABSTRACT:
A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be inserted into a memory bank insertion area, via an interconnect line which, in a preferred embodiment, may be a select line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks a type detection signal is multiplexed over the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller. Accordingly, memory systems capable of accommodating differing quantities and types of memory banks may be implemented with a single controller utilizing a single interconnect line to enable presence detection and type identification to enable the appropriate configuration thereof. In an embodiment utilizing a select line as the interconnect line, implementation of the presence and type detection may be accomplished without the addition of dedicated detect lines to the memory system.

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T. T. Dang et al., "Memory Presence Circuit for a Processor Complex", IBM Technical Disclosure Bulletin, vol. 36, No. 10, Oct. 1993, pp. 325-326.

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