Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2006-07-21
2009-06-09
Lane, Jack A (Department: 2185)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230030, C365S230080, C365S233100
Reexamination Certificate
active
07545702
ABSTRACT:
A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.
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Ashok Ambica
Kenkare Prashant
Ramaraju Ravindraraj
Freescale Semiconductor Inc.
Hill Susan C.
Lane Jack A
Singh Ranjeev
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