Communications: electrical – Digital comparator systems
Patent
1975-10-16
1977-06-07
Shaw, Gareth D.
Communications: electrical
Digital comparator systems
G06F 1300
Patent
active
040286843
ABSTRACT:
A ROM patching facility is disclosed which permits any ROM address location containing defective information to be patched. New and updated program information is supplied to the system upon the detection of each address word that is to be patched. The disclosed equipment repatches one or more times a ROM address that has already been patched. Upon the detection of each such address, the program information associated with the most recent implemented patch is returned to the system. The disclosed equipment comprises a plurality of PROM decoders for detecting ROM addresses that are to be patched and for generating output signals representing each patched address, encoders for receiving the decoder output signals and for encoding each such signal into binary address information, and auxiliary memories controlled by the encoder address information for providing valid program information to the system upon each detection of a patched ROM address.
REFERENCES:
patent: 3934227 (1976-01-01), Worst
Divine Charles Hamman
Moran John Christian
Bartz C. T.
Bell Telephone Laboratories Incorporated
Duft Donald M.
Shaw Gareth D.
LandOfFree
Memory patching circuit with repatching capability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory patching circuit with repatching capability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory patching circuit with repatching capability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1241170