Memory patching circuit with counter

Details Memory patching circuit with counter Memory patching circuit with counter

1975-10-16

1977-06-07

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 1300

Patent

active

040286835

ABSTRACT:
A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever ROM word locations containing invalid information are addressed. The disclosed arrangement uses a plurality of small capacity PROMs as a decoder to detect the receipt of each address word representing a defective ROM locaton. Upon each detection of a defective address, the decoder temporarily inhibits the output of the ROM and causes a small auxiliary memory to output valid program information as a substitute for that in the defective ROM location. A counter is used as a supplemental addressing source for both the decoder and the auxiliary memory. This increases the patching capability by subdividing the decoder and the auxiliary memory into 2.sup.n segments where n is the number of bits supplied by the counter.

REFERENCES:
patent: 3934227 (1976-01-01), Worst

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