Memory patching circuit

Details Memory patching circuit Memory patching circuit

1975-10-16

1977-06-07

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 1300

Patent

active

040286789

ABSTRACT:
A read only memory (ROM) patching arrangement is disclosed which provides valid output information whenever ROM locations containing invalid information are addressed. The disclosed arrangement detects the receipt of each ROM address word representing a defective location, temporarily inhibits the output of the ROM, and causes a small auxiliary PROM to output valid information as a substitute for that in the defective ROM location. Decoder circuitry is disclosed which uses a minimum number of small capacity PROMs to detect a limited number of ROM addresses to be patched.

REFERENCES:
patent: 3934227 (1976-01-01), Worst

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