Memory pack addressing system

Details Memory pack addressing system Memory pack addressing system

1983-03-23

1986-01-21

Popek, Joseph A.

Static information storage and retrieval

Addressing

G11C 800

Patent

active

045660824

ABSTRACT:
Disclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedback signal from the memory pack provided in response to the memory address lines. Since each memory pack excludes the chip selector circuitry, the memory packs can be made smaller in size. The memory packs are in effect self-configuring since they control the feedback of the address signals to the chip selector which generates the chip enable signals. Many types and capacities of memory packs can be mixed in the system since the pack determines the memory address space in which it resides.

REFERENCES:
patent: 4156290 (1979-05-01), Lanza

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