Memory output timing control circuit with merged functions

Details Memory output timing control circuit with merged functions Memory output timing control circuit with merged functions

2006-07-11

2006-07-11

Mai, Son (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189040, C365S200000

Reexamination Certificate

active

07075855

ABSTRACT:
An output timing control circuit for use with a memory array. The output timing control circuit includes a redundancy decode circuit and a bit column output circuit. The bit column output circuit includes a first bit column output gate and a second bit column output gate, each bit column output gate is coupled to a bitline in the memory array. A precharge circuit is coupled to an output of the first bit column output gate and the second bit column output gate. The precharge circuit is responsive to a port enable signal. The redundancy decode circuit receives the port enable signal and a fuse signal and activates one of the first bit column output gate and the second bit column output gate.

REFERENCES:
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patent: 6414892 (2002-07-01), Furumochi
patent: 6657886 (2003-12-01), Adams et al.
patent: 6737685 (2004-05-01), Aipperspach et al.
patent: 6741493 (2004-05-01), Christensen et al.
patent: 6771552 (2004-08-01), Fujisawa
patent: 2005/0007813 (2005-01-01), Adams et al.

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