Memory organizing and addressing method for digital video images

Television – Image signal processing circuitry specific to television – With details of static storage device

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Details

348718, 345200, 345203, H04N 5907

Patent

active

055858635

ABSTRACT:
A method for organizing and addressing memory of a digital video image is provided for one and two dimensional image processing using fast page mode accessing of memory, and also for displaying composite digital video images. A DRAM (12) is mapped to address locations storing segmented memory, non-segmented memory, line pointer tables, and horizontal description tables. The lines of a digital image are organized in DRAM (12) in either segmented memory or non-segmented memory. For segmented memory, each line of the image is broken up into equal line segments of pixels. Vertically aligned columns of line segments in the image are then stored in one or more rows of the DRAM (12). For non-segmented memory, each line is stored in a format where rows of DRAM (12) each represent a line of image data. To provide a means of locating the lines of the image, a line pointer table is stored in the DRAM (12) having entries corresponding to the location in memory of the start of each line of the image, and an indicator in each entry indicating whether a line is segmented or non-segmented. Two dimensional processing of an image in segmented memory is facilitated by fast page mode accessing since both vertical and horizontal pixel information is obtainable in a single row address of DRAM (12). In addition, a horizontal description table provides a means of displaying a composite image without forming the composite image in DRAM (12). Each composite image is divided into zones of rectangular pixel regions, and then separated into sets of lines having one or more zones. For each set of lines, a horizontal description table describes how the pixels in the zones for that set are to be displayed.

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