Memory organization apparatus and method

Details Memory organization apparatus and method Memory organization apparatus and method

1985-10-30

1988-05-17

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340798, 340723, G09G 116

Patent

active

047454075

ABSTRACT:
An improved memory organization for use in a computer display system including a display having a plurality of display pixels for defining images that includes: a frame buffer memory having a plurality of memory cells organized into a matrix, said memory comprising first and second maps wherein the contents of the maps correspond to the pixels and define characteristics of the pixels, the maps being defined along X and Z axes of the matric; reading means coupled to the frame buffer memory for selectively reading, in one memory cycle operation, a plurality of bits from memory cells defining one of the maps; writing means coupled to said frame buffer memory for selectively storing, in one memory cycle operation, a plurality of bits into memory cells defining one of the maps; control logic means coupled to the reading means and the writing means for generating control signals for selectively reading a plurality of bits from one of the maps and writing a plurality of bits into one of the maps to define the images to be displayed on said display; wherein multiple maps may be defined in an array of memory cells, each of the maps providing different characteristics for the pixels of the display.

REFERENCES:
patent: 3911418 (1975-10-01), Takeda
patent: 4180805 (1979-12-01), Burson
patent: 4206457 (1980-06-01), Weisbecker et al.
patent: 4475104 (1984-10-01), Shen
patent: 4496976 (1985-01-01), Swanson et al.
patent: 4509043 (1985-04-01), Mossaides
patent: 4580135 (1986-04-01), Kummer et al.
patent: 4667190 (1987-05-01), Fant

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