Memory module with load capacitance added to clock signal input

Details Memory module with load capacitance added to clock signal input Memory module with load capacitance added to clock signal input

2006-12-14

2010-02-02

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S051000, C365S149000, C365S202000

Reexamination Certificate

active

07656744

ABSTRACT:
A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.

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patent: 2005-78547 (2005-03-01), None

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