Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2009-03-20
2009-12-22
Nguyen, Tuan T (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S051000, C365S189020, C365S230030, C365S230060
Reexamination Certificate
active
07636274
ABSTRACT:
A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.
REFERENCES:
patent: 4368515 (1983-01-01), Nielsen
patent: 4392212 (1983-07-01), Miyasaka et al.
patent: 4633429 (1986-12-01), Lewandowski et al.
patent: 4670748 (1987-06-01), Williams
patent: 4958322 (1990-09-01), Kosugi et al.
patent: 4961172 (1990-10-01), Shubat et al.
patent: 4980850 (1990-12-01), Morgan
patent: 5247643 (1993-09-01), Shottan
patent: 5345412 (1994-09-01), Shiratsuchi
patent: 5426753 (1995-06-01), Moon
patent: 5483497 (1996-01-01), Mochizuki et al.
patent: 5495435 (1996-02-01), Sugahara
patent: 5581498 (1996-12-01), Ludwig et al.
patent: 5590071 (1996-12-01), Kolor et al.
patent: 5699542 (1997-12-01), Mehta et al.
patent: 5702984 (1997-12-01), Bertin et al.
patent: 5703826 (1997-12-01), Hush et al.
patent: 5745914 (1998-04-01), Connolly et al.
patent: 5802395 (1998-09-01), Connolly et al.
patent: 5805520 (1998-09-01), Anglada et al.
patent: 5822251 (1998-10-01), Bruce et al.
patent: RE36229 (1999-06-01), Cady
patent: 5926827 (1999-07-01), Dell et al.
patent: 5959930 (1999-09-01), Sakurai
patent: 5963464 (1999-10-01), Dell et al.
patent: 5966736 (1999-10-01), Gittinger et al.
patent: 6018787 (2000-01-01), Ip
patent: 6070217 (2000-05-01), Connolly et al.
patent: 6070227 (2000-05-01), Rokicki
patent: 6108745 (2000-08-01), Gupta et al.
patent: 6154418 (2000-11-01), Li
patent: 6185654 (2001-02-01), Van Doren
patent: 6209074 (2001-03-01), Dell et al.
patent: 6226709 (2001-05-01), Goodwin et al.
patent: 6408356 (2002-06-01), Dell
patent: 6414868 (2002-07-01), Wong et al.
patent: 6453381 (2002-09-01), Yuan et al.
patent: 6470417 (2002-10-01), Kolor et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6518794 (2003-02-01), Coteus et al.
patent: 6553450 (2003-04-01), Dodd et al.
patent: 6646949 (2003-11-01), Ellis et al.
patent: 6674684 (2004-01-01), Shen
patent: 6681301 (2004-01-01), Mehta et al.
patent: 6697888 (2004-02-01), Halbert et al.
patent: 6705877 (2004-03-01), Li et al.
patent: 6742098 (2004-05-01), Halbert et al.
patent: 6785189 (2004-08-01), Jacobs et al.
patent: 6807125 (2004-10-01), Coteus et al.
patent: 6813196 (2004-11-01), Park et al.
patent: 6834014 (2004-12-01), Yoo et al.
patent: 6944694 (2005-09-01), Pax
patent: 6961281 (2005-11-01), Wong et al.
patent: 6981089 (2005-12-01), Dodd et al.
patent: 6982892 (2006-01-01), Lee et al.
patent: 6982893 (2006-01-01), Jakobs
patent: 6996686 (2006-02-01), Doblar et al.
patent: 7007130 (2006-02-01), Holman
patent: 7007175 (2006-02-01), Chang et al.
patent: 7120727 (2006-10-01), Lee et al.
patent: 7124260 (2006-10-01), LaBerge et al.
patent: 7133960 (2006-11-01), Thompson et al.
patent: 7133972 (2006-11-01), Jeddeloh
patent: 7167967 (2007-01-01), Bungo et al.
patent: 7181591 (2007-02-01), Tsai
patent: 7200021 (2007-04-01), Raghuram
patent: 7266639 (2007-09-01), Raghuram
patent: 7281079 (2007-10-01), Bains et al.
patent: 7289386 (2007-10-01), Bhakta et al.
patent: 7346750 (2008-03-01), Ishikawa
patent: 7356639 (2008-04-01), Perego et al.
patent: 7437591 (2008-10-01), Wong
patent: 7471538 (2008-12-01), Hofstra
patent: 2001/0003198 (2001-06-01), Wu
patent: 2001/0052057 (2001-12-01), Lai
patent: 2002/0088633 (2002-07-01), Kong et al.
patent: 2003/0063514 (2003-04-01), Faue
patent: 2003/0090879 (2003-05-01), Doblar et al.
patent: 2003/0191995 (2003-10-01), Abrosimov et al.
patent: 2003/0210575 (2003-11-01), Seo et al.
patent: 2004/0037158 (2004-02-01), Coteus et al.
patent: 2004/0201968 (2004-10-01), Tafolla
patent: 2005/0036378 (2005-02-01), Kawaguchi et al.
patent: 2005/0281096 (2005-12-01), Bhakta et al.
patent: 2006/0044860 (2006-03-01), Kinsley et al.
patent: 2006/0117152 (2006-06-01), Amidi et al.
patent: 2006/0126369 (2006-06-01), Raghuram
patent: 2006/0129755 (2006-06-01), Raghuram
patent: 2006/0179206 (2006-08-01), Brittain et al.
patent: 2006/0267172 (2006-11-01), Nguyen et al.
patent: 2006/0277355 (2006-12-01), Ellsberry et al.
patent: WO 92/02879 (1992-02-01), None
patent: WO 94/07242 (1994-03-01), None
patent: WO 95/34030 (1995-12-01), None
patent: WO 02/058069 (2002-07-01), None
patent: WO 03/017283 (2003-02-01), None
patent: WO 03/069484 (2003-08-01), None
patent: WO 2006/055497 (2006-05-01), None
“64 & 72 Pin Zip/Simm Sram Module,” JEDEC, Standard No. 21-C, www.jedec.com/download/search/4.04—01.pdf, Jun. 1997 pp. 4.4.1-1.
Abali, B. “Memory Expansion Technology (MXT): Software Support and Performance,” IBM J. Res. & Dev., vol. 45, No. 2, 2001, pp. 287-300.
Arlington, DL Evans. “Enhancement of Memory Card Redundant Bit Usage Via Simplified Fault Alignment Exclusion,” IMB Technical Disclosure Bulletin, 1987.
Arroyo et al. “Method of executing Manufacturing ROM Code Without Removing System Roms,” IP.com, IPCOM000037214D, 1989.
“Bank Striping of Data Across Internal SDRAM Banks,” IP.com, IPCOM000013697D, 2000.
Barr, Michael. “Programmable Logic: What's it to Ya?,” Embedded Systems Programming, Jun. 1999, pp. 75-84.
Bennayoun et al. “Input/Output Chip Select Doubler,” IBM Technical Disclosure Bulletin, vol. 38, No. 04 1995, pp. 237-240.
Blum et al. “Fast Multichip Memory System With Power Select Signal,” IMB Technical Disclosure Bulletin, 1979.
Cuppu et al. “A Performance Coparison of Contemporary DRAM Architectures,”IEEE Proceedings of the 26thInternational Symposium on Computer Architectures, May 2-4, 1999, Atlanta, Geogia, pp. 1-12.
Cuppu et al. “Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance?,” IEEE, 2001, pp. 62-71.
Cuppu et al. “High-Performance DRAMs in Workstation Environments,” IEEE Transactions on Computers, vol. 50, No. 11, 2001, pp. 1133-1153.
Denneau, M. “Logic Processor For Logic Simulation Machine,” IBM Technical Disclosure Bulletin, vol. 25, No. 1, 1982.
“Distributed Memory Mapping,” IP.com, IPCOM000014788D, 2000.
Fairchild Semiconductor. “DM74LS138 DM74LS139 Decoder/Demultiplexer,” Fairchild Semiconductor Corporation, 2000.
Fitzgerald et al. “Chip Select Circuit for Multi-Chip RAM Modules,” IP.com, IPCOM000044404D, 1984.
Gray, KS. “Fet Ram Chip Double Density Scheme,” IP.com, IPCOM000043942D, 1984.
Grimes et al. “Access Rate/Availability Improvement Logic for Dynamic Memories,” IBM Technical Disclosure Bulletin, Oct. 1982.
Gupta et al. “Designing and Implementing a Fast Crossbar Scheduler,” IEEE Micro, 1999, pp. 20-28.
Hession et al. “Chip Select Technique for Multi Chip Decoding,” IP.com, IPCOM000070404D, 1985.
Hewlett-Packard. “Memory technology evolution: an overview of system memory technologies,” technology brief, 7th edition. 2003.
Hoare et al. “An 88-Way Multiprocessor Within An FPGA With Customizable Instructions,” Proceedings of the 18th International Parallel and Distributed Processing Symposium, 2004.
“Information Huawei or FPGA-Take Five,” Electronic News, 2002, p. 24.
Intel Corporation, PC SDRAM Registered DIMM Design Support Document, Revision 1.2, Oct. 1998.
Intel Corporation, 66/100 MHz PC SDRAM 64-Bit Non-ECC/Parity 144 Pin Unbuffered SO-DIMM Specification, Revision 1.0, Feb. 1999.
JEDEC Standard No. 21-C, 4.20-2—168 Pin, PC133 SDRAM Registered Design Specification, Revision 1.4, Release 11a, Feb. 2002.
JEDEC Standard No. 21-C, 4.20-2—168 Pin, PC133 SDRAM Registered SO-DIMM, Reference Design Specification, Revision 1.02, Release 11. Published Oct. 20
Bhakta Jayesh R
Solomon Jeffrey C
Knobbe Martens Olson and Bear LLP
Netlist, Inc.
Nguyen Tuan T
Sofocleous Alexander
LandOfFree
Memory module with a circuit providing load isolation and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory module with a circuit providing load isolation and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory module with a circuit providing load isolation and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4103690