Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-05-16
2001-07-24
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S052000, C365S230030
Reexamination Certificate
active
06266265
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory modules and more specifically to a memory module in which timing differences among memory units are eliminated by balancing their parasitic capacitive loads.
2. Description of the Related Art
As shown in
FIG. 1
, the current semiconductor memory module is comprised of a plurality of integrated-circuit memory units (packages) divided into two groups according to clock pulse sequences supplied from clock terminals CLK
0
and CLK
1
. For one thing, memory modules do not necessarily have an even-number of memory units, the clock groups have different numbers of memory units. In
FIG. 1
, nine memory units U
0
to U
8
are shown divided into a first group of chips U
0
to U
4
and a second group of chips U
5
to U
8
, the first group being driven by clock pulses from terminal CLK
0
and the second group by clock pulses from terminal CLK
1
. Further, design considerations may dictate that memory units are divided into a plurality of clock groups so that each group may have a different number of memory units from other groups.
Because of the high clock frequency, the lines connecting the clock terminals CLK
0
and CLK
1
to the clock inputs of the respective memory units can be considered as transmission lines involving parasitic capacitance. To minimize the differences in parasitic capacitance among the memory units, the clock lines are patterned so that they have equal length. However, the clock source of the terminal CLK
0
is required to drive one memory unit greater than is required for the clock source of terminal CLK
1
. This difference in load between the clock sources causes a time delay At between the point at which the rising edge of the CLK
1
pulse passes the threshold and the point at which the rising edge of the CLK
0
clock pulse passes the threshold as shown in FIG.
2
. Setup time and hold time are defined. The setup time (tS) starts when a signal changes state and lasts until the rising edge of a clock pulse crosses the threshold and the hold time (tH) starts when the clock pulse crosses the threshold and lasts until the signal changes state. The time window “tWindow” (which is equal to the sum of the setup and hold times) of clock source CLK
0
is delayed by At with respect to the time window of clock source CLK
1
and hence the total time window tWindow is lengthened by &Dgr;t. This is undesirable from the performance viewpoint since it reduces the operating margin of the module. Furthermore, the clock skew &Dgr;t causes the access time (tAC) and data hold time (tOH) for output data of each clock group to differ from those of the other clock group.
In order to overcome the clock-skew problem, Intel's PC
100
memory module includes a dummy capacitor
10
, which is connected to the clock terminal CLK
1
, as shown in FIG.
3
. Since the value of this capacitor is equal to the capacitance which the clock input of each memory unit has, the load capacitance of each clock source is balanced with the load capacitance of the other clock source. However, since the load capacitance of the clock input of each memory unit depends largely on design, production process and operating voltage, it is difficult to precisely determine the value of the dummy capacitor.
Similar problem occurs with memory modules in which data mask signals (DQMB) are used to drive its memory units. As shown in
FIG. 4
, memory units U
3
and U
4
are driven by a common data mask signal DQMB
3
, while the other memory units are individually driven by respective data mask signals. Parasitic capacitive load imbalance exists between the combined capacitance of memory units U
3
and U
4
and the individual capacitance of each of the other memory units.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a memory module in which balanced parasitic capacitive loads are established with immunity to external factors such as operating characteristics and device variability.
According to a broader aspect, the present invention provides a memory module comprising first and second integrated-circuit memory units, each including a control pin terminal and a third integrated-circuit memory unit including a vacant pin terminal and a control pin terminal. A first plurality of connections are provided for receiving a control signal from an external source and supplying the received signal to the control pin terminal of the first and second memory units. A second plurality of connections receive and supply the control signal to the control pin terminal of the third memory unit and the vacant pin terminal. Preferably, the third memory unit includes a circuit equivalent in operating characteristics to a circuit connected to the control pin terminal, and the vacant pin terminal is connected to the equivalent circuit.
According to a second aspect, the present invention provides a memory module comprising a first group of integrated-circuit memory units, each including a control pin terminal, and a second group of integrated-circuit memory units each including a control pin terminal. At least one of the memory units of the second group further includes at least one vacant pin terminal. A first plurality of connections receive a control signal from an external source and supply the received signal to the control pin terminal of each of the first group of memory units. A second plurality of connections receive and supply the control signal to the control pin terminal of each of the second group of memory units and to at least one vacant pin terminal of the second group of memory units. Preferably, the vacant pin terminal is connected to a circuit equivalent in operating characteristics to a circuit connected to the control pin terminal.
According to a third aspect, the present invention provides a memory module comprising a plurality of integrated-circuit memory units, each including a vacant pin terminal and a control pin terminal, and at least two integrated-circuit memory units, each of the two memory units including a control pin terminal. A plurality of connections are provided for receiving a plurality of control signals and respectively supplying the received signals to the control pin terminal of the plurality of memory units and a second connection for receiving a control signal and supplying the received control signal to the control pin terminal of the two memory units.
REFERENCES:
patent: 5357624 (1994-10-01), Lavan
patent: 5867448 (1999-02-01), Mann
patent: 6026007 (2000-02-01), Jigour et al.
patent: 6049476 (2000-04-01), Laudon et al.
Ho Hoai V.
McGuireWoods LLP
NEC Corporation
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