Memory module, method for using same and memory system

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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Details

C365S052000, C365S063000, C257S777000, C257S780000, C326S026000, C326S030000

Reexamination Certificate

active

08064236

ABSTRACT:
In a multi-rank memory module having a terminal resistance of a data input/output pad13and a terminal resistance control pad14that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad14of a memory chip12, having a longer length of an interconnect between a data bus19on a module substrate8and a data input/output pad13, is connected to a terminal resistance control interconnect18or21to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip11, having a shorter length of an interconnect between the data bus19on the module substrate and the data input/output pad13, is connected to a fixed potential20to turn on the terminal resistance.

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patent: 7342411 (2008-03-01), Vergis et al.
patent: 7928757 (2011-04-01), Nguyen et al.
patent: 2005/0270875 (2005-12-01), Saeki
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patent: 2007-164787 (2007-06-01), None
patent: 2008-46797 (2008-02-01), None

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