Memory module having module control circuit

Details Memory module having module control circuit Memory module having module control circuit

1998-10-23

2000-08-08

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523008, G11C 800

Patent

active

061011495

ABSTRACT:
A memory module having a module control circuit which is capable of decreasing an operational current by configuring a 1BANK 4M.times.64 module using 16M DRAMs (1K Refresh.times.16) and reducing the number of operational devices. The module control circuit decodes externally inputted eleventh and twelfth address signals and outputs control signals in accordance with one of a plurality of column address strobe signals and a row address strobe signal, and a plurality of DRAMs in a memory unit are selected by the control signals from the module control circuit and are parallely connected for performing a data write and read operation in accordance with externally inputted first through tenth address signals, a write enable signal, an output enable signal, and the column address strobe signals.

REFERENCES:
patent: 5283877 (1994-02-01), Gastinel et al.
patent: 5319591 (1994-06-01), Takeda et al.
patent: 5367526 (1994-11-01), Kong
patent: 5646904 (1997-07-01), Ohno et al.
patent: 5912860 (1999-06-01), Schaefer

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