Memory module having data switcher in high speed memory device

Details Memory module having data switcher in high speed memory device Memory module having data switcher in high speed memory device

2000-07-14

2002-06-18

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S240000

Reexamination Certificate

active

06407962

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a memory module having a data switcher in a double data rate (DDR) synchronous dynamic random access memory (DRAM) device, which is capable of reducing loads of a common data bus line.
DESCRIPTION OF THE PRIOR ART
For achieving a high speed of operation in a dynamic random access memory (DRAM), synchronous DRAM (SDRAM) has been developed which operates in synchronization with an external clock. The SDRAM includes a single data rate (SDR) SDRAM, and a double data rate (DDR) SDRAM.
While the SDRAM operates in synchronization with rising edges of an external clock, the DDR SDRAM operates in synchronization with rising and falling edges of an external clock. Therefore, compared with the SDR SDRAM, the DDR SDRAM can achieves a higher speed of operation without increasing a frequency of the external clock.
FIG. 1
is a block diagram showing a conventional memory module having a plurality of memory chips.
As shown, a conventional memory module is provided by incorporating a plurality of memory chips
11
to
13
and a memory controller
14
on one board
10
. The memory chips
11
to
13
are connected to a common data bus line such as a global input/output line. In a read operation, when a specific memory chip is selected in response to a chip select signal which is outputted from the memory controller
14
, data stored in the selected memory chip is outputted to an external circuit via the common data bus line.
However, when one memory chip is selected, unselected memory chips are still being connected to the common data bus line, so that loads of the common data bus line are increased. Especially, in a high speed memory device such as DDR SDRAM using a high frequency, the increased loads deteriorate a characteristic of operation speed.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a high speed memory device having a data switcher, in which loads of a common data bus line are reduced.
In accordance with an aspect of the present invention, there is provided an apparatus for generating a switcher control signal in a memory module having a plurality of memory chips and a plurality of data switchers on one board, each data switcher being selectively turned on or off in response to the switcher control signal to connect corresponding memory chip with a common data bus line, comprising: a plurality of shift counting means for shift counting a write command signal in response to an internal clock signal and a reset signal, to generate a plurality of shift counting signals; a switcher enable control signal generating means for receiving the shift counting signals to generate a switcher enable control signal for enabling the switcher control signal during a predetermined time corresponding to a burst length; a pull down driving means for pulling down the switcher control enable signal to generate a pull-down signal; and an output means for outputting the switcher control signal in response to the pull-down signal.
In accordance with another aspect of the present invention, there is provided a memory module used in a high speed memory device, comprising: a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) chips having a switcher control signal generator for generating a switcher control signal; and a plurality of data switchers, wherein each data switcher is selectively turned on or off in response to the switcher control signal to connect corresponding memory chip with a command data bus line, wherein each data switcher including: a plurality of shift counting means for shift counting a write command signal in response to an internal clock signal and a reset signal, to generate a plurality of shift counting signals; a switcher enable control signal generating means for receiving the shift counting signals to generate a switcher enable control signal for enabling the switcher control signal during a predetermined time corresponding to a burst length; a pull down driving means for pulling down the switcher control enable signal to generate a pull-down signal; and an output means for outputting the switcher control signal in response to the pull-down signal.


REFERENCES:
patent: 5703828 (1997-12-01), Park et al.
patent: 5715211 (1998-02-01), Toda
patent: 6314033 (2001-11-01), Sugamoto et al.
patent: 2348722 (2000-10-01), None

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