Memory module and memory system

Details Memory module and memory system Memory module and memory system

2006-12-06

2008-08-12

Mai, Son L (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S052000

Reexamination Certificate

active

07411806

ABSTRACT:
A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

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Japanese Office Action, dated Mar. 20, 2007, from corresponding Japanese patent application 2002-222771.
Naono et al., “First design of high-speed memory system using direct RAM bus technology”, Interface, Japan, CQ Publishing Co., Apr. 1, 1999, vol. 25, No. 4, pp. 183-193.
Agata et al., “Differential clock transmission method in large-capacity DRAM”, 1992, Institute of Electronics, Information and Communication Engineers, Autumn convention collection of presentations [vol. 5], Japan, Institute of Electronics, Information and Communication Engineers, Sep. 15, 1992, p. 5-150.
English translation for Naono et al., “First design of high-speed memory system using direct RAM bus technology”, Interface, Japan, CQ Publishing Co., Apr. 1, 1999, vol. 25, No. 4, pp. 183-193.
English translation for Agata et al., “Differential clock transmission method in large-capacity DRAM”, 1992, Institute of Electronics, Information and Communication Engineers, Autumn convention collection of presentations [vol. 5]Japan, Institute of Electronics, Information and Communication Engineers, Sep. 15, 1992, p. 5-150.

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