Memory module and memory system

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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Details

C365S189011, C365S051000

Reexamination Certificate

active

07123497

ABSTRACT:
In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. In this constitution, a wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

REFERENCES:
patent: 6133640 (2000-10-01), Leedy
patent: 2002/0036338 (2002-03-01), Matsuo et al.
patent: 2004/0080013 (2004-04-01), Kimura et al.
patent: 2005/0082664 (2005-04-01), Funaba et al.
patent: 2005/0139978 (2005-06-01), Hirose
patent: 6-291250 (1994-10-01), None
patent: 9-504654 (1997-05-01), None
patent: 2001-256772 (2001-09-01), None

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