Memory module and impedance calibration method of...

Details Memory module and impedance calibration method of... Memory module and impedance calibration method of...

2007-09-11

2007-09-11

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S052000, C365S201000

Reexamination Certificate

active

11082551

ABSTRACT:
Disclosed is a memory module and a method of calibrating an impedance of a semiconductor memory device of the memory module, where the memory module includes semiconductor memory devices each having a separate terminal for calibrating impedance characteristics, and a reference resistor commonly connected to the separate terminals, such that the number of reference resistors used in calibration of impedance characteristics of an off-chip driver or an on-die termination circuit of the semiconductor memory device is reduced.

REFERENCES:
patent: 6484232 (2002-11-01), Olarig et al.
patent: 6791865 (2004-09-01), Tran et al.
patent: 6958613 (2005-10-01), Braun et al.
patent: 07-240498 (1995-09-01), None
patent: 2002-023901 (2002-01-01), None
patent: 2002-237180 (2002-08-01), None

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