Memory, memory operating method, and memory system

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185050

Reexamination Certificate

active

07889568

ABSTRACT:
A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.

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patent: 7116583 (2006-10-01), Sander et al.
patent: 7212443 (2007-05-01), Furuyama
patent: 7466596 (2008-12-01), Ausserlechner et al.
patent: 2005/0270851 (2005-12-01), Kato et al.
patent: 2007/0285984 (2007-12-01), Kato et al.
patent: 2004-199837 (2004-07-01), None
patent: 2005-346819 (2005-12-01), None

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