Memory mapping unit

Details Memory mapping unit Memory mapping unit

1981-11-17

1983-08-23

Chan, Eddie P.

Boots, shoes, and leggings

365 63, G06F 1300, G11C 506, G11C 700

Patent

active

044007949

ABSTRACT:
A memory mapping unit enables different sized memory boards to be mapped in any order into any size memory address boundary in a microprocessor. Any 2.sup.K sized memory board (where N.ltoreq.K.ltoreq.M) can be mapped to any 2.sup.N address boundary. To accomplish this, a binary adder adds the 2's complement of the base address register with significant bits from the address buss. A series of logic gates are connected to the output of the binary adder and a board size mask register. The logic gates perform an "AND" operation on the output from the binary adder and the board size mask register. The outputs from the logic gates connect to a multiple input "NOR" gate. When all the inputs are logical "zero", indicating the address is on the board, a board enable command is produced which activates the memory board transceiver.

REFERENCES:
patent: 4025903 (1977-05-01), Kaufman et al.
patent: 4121286 (1978-10-01), Venton et al.
patent: 4189767 (1980-02-01), Ahuja
patent: 4330825 (1982-05-01), Girard

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