Memory management unit for the MIL-STD 1750 bus

Details Memory management unit for the MIL-STD 1750 bus Memory management unit for the MIL-STD 1750 bus

1988-10-25

1992-01-07

Shaw, Gareth D.

Boots, shoes, and leggings

3649705, 364969, 364957, 3649571, 3649481, 364970, 364DIG2, G06F 1206

Patent

active

050797379

ABSTRACT:
A single-chip memory management unit automatically operates in either 1750A or 1750B mode as required, including the provision of memory management and/or block protection, with the added feature of on-chip arbitration between two bus masters that may be either independent of the CPU or controlled by the CPU.

REFERENCES:
patent: 3742458 (1973-06-01), Inoue et al.
patent: 4368515 (1983-01-01), Nielsen
patent: 4432067 (1984-02-01), Nielsen
patent: 4473877 (1989-09-01), Tulk
patent: 4485457 (1984-11-01), Balaska et al.

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