Memory management for microprocessor system

Details Memory management for microprocessor system Memory management for microprocessor system

1988-04-19

1990-11-20

Shaw, Gareth D.

Boots, shoes, and leggings

3642563, 3642564, 3642434, 36424341, 3642328, G06F 1210

Patent

active

049723383

ABSTRACT:
Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level. eyboard

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