Memory management circuit which provides simulated privilege lev

Details Memory management circuit which provides simulated privilege lev Memory management circuit which provides simulated privilege lev

1995-09-01

1997-11-04

Beausoliel, Jr., Robert W.

395733, G06F 1100

Patent

active

056849486

ABSTRACT:
A memory management unit provides security functions for a processor which has no specialized hardware support for a memory management unit. An exception security system is provided for use with an exception-capable processor. In an unsecure mode, the processor responds to an exception by retrieving unprotected exception information from generally accessible exception information register circuitry and executes an exception processing routine indicated by the unprotected exception information. Secure exception information register circuitry is provided in the memory management unit that holds a protected copy of exception information. Exception detection circuitry within the memory management unit detects an exception and causes the secure exception information register circuitry to provide the protected copy of the exception information to the processor in place of the unprotected exception information which would otherwise be provided to the processor from the generally accessible exception information register circuitry. Thus, the processor executes an exception routine indicated by the protected copy of the exception information and not an exception routine indicated by the unprotected exception information. In order to simulate processor privilege levels for each of a plurality of processor address space segments, current privilege level circuitry holds a current privilege level access indication, and programmable circuitry associated with each of the address space segments holds a privilege level access indication associated that address space segment. Access validation circuitry determines which of the address space segments is being accessed by the processor and compares the current privilege level access indication with the privilege level access indication associated with the address space segment being addressed. The access validation circuitry includes violation indication means, accessible by the processor, that indicates a result of the comparison. Preferably, current privilege level circuitry is provided which holds a current privilege level indication and which also includes stack circuitry that holds a plurality of security level indications.

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