Memory macro and semiconductor integrated circuit

Details Memory macro and semiconductor integrated circuit Memory macro and semiconductor integrated circuit

2003-11-06

2004-12-14

Clark, S. V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S208000

Reexamination Certificate

active

06831356

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory macro such as an SRAM, and a semiconductor integrated circuit such as a system LSI provided with a plurality of macros including a memory macro. “A memory macro” may be design data corresponding to a memory block which design data is used for generating semiconductor integrated circuit layout data, or a block on a semiconductor integrated circuit which block corresponds to the design data.
2. Prior Art
Semiconductor integrated circuits have ever-increasing in scale, various kinds of macros constituting a system are placed together thereon, and semiconductor integrated circuits have been increasingly constructed as one chip as a system LSI. Memory circuits are no exception. Moreover, the memory capacity used on system LSIs tends to increase, particularly, with increase in image processing. This is more conspicuous in the case of SRAM macros suitable for high-speed processing such as image processing.
Examples of the various kinds of macros include analog circuits such as PLL circuits and AD/DA converters, and interface circuits such as USB and IEEE 1394. Moreover, digital circuits such as microcomputer blocks are sometimes expressed as one macro on larger-scale system LSIs. For example, blocks in a logic circuit
40
of
FIG. 9
correspond to macros.
In the development of system LSIs, with respect to such various kinds of macros such as memory macros, it is typical that, first, development is performed for ensuring the performance of each individual macro and in the highest development of system LSIs, various kinds of macros are placed together at the same time.
FIG. 11
shows a typical memory macro and wirings around terminals of the memory macro (see, for example, Japanese Laid-Open Patent Application No. H11-134870). In
FIG. 11
, reference numeral
1
represents the memory macro, and reference numeral
2
represents terminals serving as contacts with the outside. The number of terminals
2
is the same as the number of signal lines necessary for the operation of the memory macro
1
. Reference numeral
3
represents wirings (external wirings) connecting the terminals
2
to macros other than the macro
1
. The memory macro
1
frequently shares signal lines with a plurality of other memory macros, and the arrangement is frequently as shown in FIG.
11
. The macros other than the memory macro
1
are other memory macros and memory controllers controlling these memory macros. Memories cannot operate unless at least connected to a control circuit such as a memory controller. Further, there are cases where a plurality of memories are connected together with a data bus being shared thereamong.
Reference numerals
4
and
5
represent power lines and ground lines (intra-memory-macro wirings) being present in the memory macro
1
and supplying charges necessary for the operation of the circuits of the memory macro
1
. The power lines and ground lines
4
and
5
have a power potential and a ground potential, respectively, and are arranged so as to form meshes inside the memory macro
1
. Wirings of the same potential are connected together. The power lines and ground lines
4
and
5
are capable of connecting with power lines and ground lines outside the memory macro
1
at the ends of the memory macro
1
. From that characteristic, a wiring layer of a high layer of the layers being used is frequently used. Reference designation S
1
represents a region width of the wirings
3
present outside the memory macro
1
.
As shown in
FIG. 11
, the memory macro
1
comprises the terminals
2
, and the power lines and ground lines
4
and
5
. At this level, this structure is supplied as the memory macro
1
for forming a system LSI. The wirings
3
are placed by the development of a high layer outside the memory macro
1
. To ensure the operation of the memory macro
1
, in many cases, wiring patterns on other layers not used by the memory macro
1
are not admitted on the memory macro
1
.
However, in the structure as shown in
FIG. 11
, since the positions of the terminals
2
are fixed, there is a restriction on the pattern of the wirings
3
, and a region area with a width S
1
is occupied as shown in FIG.
11
. This region is proportional to the number of wirings. Consequently, when the capacity of the memory macro
1
increases, the number of wirings increases, and the occupied area tends to increases. For example, in the case of a several-megabit-class SRAM, in some structures, the number of wirings
3
is several tens, and compared to the area of the memory macro
1
, the wirings
3
occupy several to a dozen or so percent thereof.
Further, since wirings on the memory macro
1
in other layers are indispensable as mentioned above, in many cases, the memory macro
1
itself is a restriction on the wiring when the floor plan of the system LSI is examined. In these cases, the area of the memory macro
1
itself tends to increase as the memory capacity increases, and its restriction is extremely large. Consequently, a wiring detouring around the memory macro
1
is required, and this increases the wiring region and causes performance deterioration due to increase in wiring length.
These problems attributable to the memory macro
1
are caused because the memory macro
1
is developed independently of the development of the system LSI. However, there are cases where the memory macro
1
is mounted on a plurality of system LSIs, and it is, conversely, inefficient to develop a memory macro
1
optimized for each individual system LSI.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a memory macro and a semiconductor integrated circuit capable of reducing the area occupied by the wirings on high layers without any versatility degradation.
Another object of the present invention is to provide a memory macro and a semiconductor integrated circuit capable of reducing a restriction on the wirings in a high level (chip level) without any versatility degradation.
To achieve the above-mentioned objects, the present invention provides a memory macro and a semiconductor integrated circuit considering development in the high level and provided with versatility.
Specifically, a memory macro and a semiconductor integrated circuit considering development in the high level are provided.
This includes:
1. optimization of interface wirings between the memory macro and external circuits; and
2. provision of feed through wiring regions passing over the memory macro.
That is, in 1, wirings disposed in the high level are previously taken in the memory macro to thereby reduce the wiring region. Moreover, area reduction is realized by supplying a memory macro with an improved degree of freedom of the wiring patterns in the high level.
Further, in 2, by providing passage wiring regions on the memory macro while ensuring the performance of the memory macro, improvement of the performance as a system LSI and area reduction are realized.
A memory macro according to a first aspect of the invention comprises: a memory array portion; an interface circuit serving as an interface of the memory array portion; and a wiring region connecting the memory array portion to the interface circuit. Mesh power wirings comprising first and second wiring layers are provided on the memory array portion. The interface circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the interface circuit or the wiring region, through an intermediate wiring comprising the second wiring layer. A region where the intermediate wiring is provided comprises a region on the memory array portion or on the wiring region. The mesh power wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided. The region where the intermediate wiring is provided sometimes includes on the interface circuit.
According to this structure, the interface circuit is connected to the plurality of signal lines comprising t

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