Memory-logic semiconductor device

Details Memory-logic semiconductor device Memory-logic semiconductor device

2000-12-29

2003-03-04

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S185050, C365S185110, C365S049130, C365S072000, C365S185010

Reexamination Certificate

active

06529397

ABSTRACT:

This application is based on Japanese Patent Application 2000-155585, filed on May 26, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of basic units each containing a memory cell and a logic cell on the same semiconductor substrate.
b) Description of the Related Art
A content addressable memory (CAM) has become noteworthy in order to realize high sophistication and high speed of an information processing system. CAM has the function that a logic cell can detect a match between the contents stored in a memory cell and externally supplied data. The memory cell is generally made of an SRAM.
One of the present inventors has proposed a CAM having the structure that the memory cell is made of a dynamic random access memory (DRAM). With this structure, a memory cell of the basic unit can be made of two access transistors, two capacitors, and four search/compare transistors (for a ternary CAM). However, the most efficient structure of CAM and its manufacture techniques are not still established.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor device having a plurality of basic units each containing a memory cell and a logic cell on the same semiconductor substrate, the device being easy to be manufactured with high integration.
Another object of the invention is to provide a semiconductor device capable of realizing a high performance CAM.
According to one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate and a plurality of basic units formed on the semiconductor substrate each having a memory element and a logic element and a same plan layout or a bilateral symmetry layout, the basic unit comprising: an isolation insulating region formed on a surface of the semiconductor substrate for defining first and second active regions; a transfer transistor having a first gate electrode formed traversing the first active region and a pair of first source/drain regions formed on both sides of the first gate electrode in the first active region; a word line connected to the first gate electrode; a bit line connected to one of the pair of first source/drain regions; a serially connected transistor having second and third gate electrodes formed traversing the second active region, a connection node formed between the second and third gate electrodes in the second active region, and a pair of second source/drain regions formed outside the second and third gate electrodes; a first signal line connected to one of the pair of second source/drain regions; a second signal line connected to the other of the pair of second source/drain regions; a third signal line connected to the second gate electrode; a storage electrode formed in an area above the other of the pair of first source/drain regions and at least a portion of the third gate electrode; a capacitor dielectric film formed on a surface of the storage electrode; a first conductive connection member formed on and under the storage electrode for connecting the storage electrode to the other of the pair of first source/drain regions; and a second conductive connection member formed on and under the storage electrode for connecting the storage electrode to the third gate electrode.


REFERENCES:
patent: 4247919 (1981-01-01), White, Jr. et al.
patent: 4791606 (1988-12-01), Threewitt et al.
patent: 5146300 (1992-09-01), Hamamoto et al.
patent: 5153685 (1992-10-01), Murata et al.
patent: 5196910 (1993-03-01), Moriuchi et al.
patent: 5374579 (1994-12-01), Kuroda
patent: 5432356 (1995-07-01), Imamura
patent: 5466621 (1995-11-01), Hisamoto et al.
patent: 5933363 (1999-08-01), Shindo
patent: 5949696 (1999-09-01), Threewitt
patent: 6038170 (2000-03-01), Shiba
patent: 6072711 (2000-06-01), Kang
patent: 6291847 (2001-09-01), Ohyu et al.
patent: 6320777 (2001-11-01), Lines et al.
patent: 3-166761 (1991-07-01), None
patent: WO/00/60604 (2000-10-01), None
Specification of co-pending U.S. Application No. 09/749,463, filed on Dec. 28, 2000, by Shigetoshi Takeda, et al.
Lines, et al., “66 MHz 2.3M Ternary Dynamic Content Addressable Memory”, IEEE Int. Workshop on Memory Technology, Design and Testing, Aug. 7-8, 2000; pp. 101-105.
European Search Report dated Sep. 6, 2001.

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