Memory interleaving in a high-speed switching environment

Details Memory interleaving in a high-speed switching environment Memory interleaving in a high-speed switching environment

2007-07-24

2007-07-24

Pezzlo, John (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S429000, C710S052000

Reexamination Certificate

active

10359817

ABSTRACT:
In one embodiment of the present invention, a system for memory interleaving in a high-speed switching environment includes multiple memory units that each include one or more memory devices. The system also includes multiple port modules. Each port module can receive a packet communicated from a component of a communications network, write the received packet to one or more of the memory units, and read a packet from one or more of the memory units for communication to the component of the communications network. The system also includes an interconnection network including a hierarchical structure that includes one or more switching stages. The interconnection network couples the memory units to the port modules such that each of the port modules can write to each of the memory units according to a first schedule and read from each of the memory units according to a second schedule and such that a first port module can read a first portion of a packet from one or more memory units for communication to a first component of the communications network before a second port module has received a second portion of the packet communicated from a second component of the communications network.

REFERENCES:
patent: 5941952 (1999-08-01), Thomas et al.
Cyriel Minkenberg and Ton Engbersen, “A Combined Input and Output Queued Packet-Switched System Based on PRIZMA Switch-on-a-Chip Technology,” IEEE Communications Magazine, pp. 70-77, Dec. 2000.
James P. G. Sterbenz and Joseph D. Touch, “High-Speed Networking,” 5 pages, 2001.
Abhijit K. Choudhury and Ellen L. Hahne, “Dynamic Queue Length Thresholds for Shared-Memory Packet Switches,” IEEE/ACM Transactions on Networking, , vol. 6, No. 2, pp. 130-140, Apr. 1998.
M. Shreedhar and George Varghese, “Efficient Fair Queuing using Deficit Round Robin,” pp. 1-21, Oct. 16, 1995.

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