Memory interface with automatic delay state

Details Memory interface with automatic delay state Memory interface with automatic delay state

1985-04-01

1986-12-23

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1338

Patent

active

046316590

ABSTRACT:
A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.

REFERENCES:
patent: 3818459 (1974-06-01), Vrablik
patent: 4040027 (1977-02-01), van Es et al.
patent: 4047245 (1977-09-01), Knipper
patent: 4095265 (1978-06-01), Vrba
patent: 4112490 (1978-09-01), Pohlman et al.
patent: 4435757 (1984-03-01), Pross, Jr.

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