Static information storage and retrieval – Addressing – Multiplexing
Reexamination Certificate
2006-11-28
2006-11-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Multiplexing
C365S230080, C365S230010
Reexamination Certificate
active
07142477
ABSTRACT:
A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases. This will essentially reduce the cycle time between a read and write memory access, and proves useful when maximizing the data throughput across the data bus when implementing double data rate (QDR) mechanisms.
REFERENCES:
patent: 6026050 (2000-02-01), Baker et al.
patent: 2002/0023200 (2002-02-01), Ryan et al.
patent: 2002/0054532 (2002-05-01), Ooishi et al.
“General DDR SDRAM Functionality,” © 2001 Micron Technology, Inc., pp. 1-11.
Parameswaran Suresh
Tran Thinh
Tzou Joseph
Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Elms Richard
Nguyen N
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