Memory interface optimized for stacked configurations

Details Memory interface optimized for stacked configurations Memory interface optimized for stacked configurations

2004-09-03

2009-08-25

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S678000, C257S684000, C257S691000, C257S737000, C711S157000, C711S219000

Reexamination Certificate

active

07579683

ABSTRACT:
A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of the memory die within a given range of sizes.

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patent: 6093942 (2000-07-01), Sei et al.
patent: 6235554 (2001-05-01), Akram et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6605875 (2003-08-01), Eskildsen
patent: 2003/0067059 (2003-04-01), Corisis
patent: 2004/0201563 (2004-10-01), Kobayashi

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