Patent
1994-03-22
1996-03-26
Elmore, Reba I.
395490, G06F 1312
Patent
active
055028349
ABSTRACT:
A memory interface apparatus includes: a pipeline register holding a data packet from a transmission path to provide an instruction code, a generation number, and data separately; a memory access unit accessing an image memory according to the instruction code, a circuit latching the output of the image memory; an ALU carrying out an operation specified by the instruction code from the pipeline register between data from the pipeline register and the output of the latch circuit for output of the operation result; a selector responsive to a select signal for selecting one of data from the pipeline register and the output of the ALU to apply the selected result to the image memory as data; an output unit generating a data packet including a result of a series of complex operation carried out by the pipeline register, the image memory, and the ALU for output; a transmission control unit controlling transmission of a data packet on the transmission path carried out by the pipeline register and the output unit; and a control unit responsive to the instruction code from the pipeline register for controlling the ALU, the memory access unit, the image memory, the latch circuit, the selector, the output unit, and the transmission control unit so that a series of complex operation processing including an access to the image memory specified by the instruction code is carried out.
REFERENCES:
Kanekura, Hiroshi and Miyata, Souichi. An Evaluation of Parallel-Processing in the Dyanamic Data-Driven Processors.
Arata Katsumi
Muramatsu Tsuyoshi
Yoshida Shin'ichi
Elmore Reba I.
Sharp Kabushiki Kaisha
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