Memory integrated circuit device including a memory having a con

Details Memory integrated circuit device including a memory having a con Memory integrated circuit device including a memory having a con

1999-01-07

2000-10-10

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518908, 365220, 36518912, G11C 800

Patent

active

061308528

ABSTRACT:
Registers are arranged along at least opposite two sides of the four sides of a dynamic random access memory cell array. The registers are interconnected via an internal data bus line used for internal data transfer for the memory cell array. At least one register of the registers arranged along the opposite two sides is coupled with an external data bus, and the other register is coupled with an internal circuit via an internal data bus. An external controller which controls an operation in response to an external control signal is provided for the register coupled with an external circuit. An internal controller which controls an operation according to a control signal from the internal circuit is provided for the register coupled with the internal circuit. The external and internal circuits are permitted to simultaneously access the memory cell array only when the external and internal circuits read the data of a memory cell located at the same address of the memory cell array.

REFERENCES:
patent: 5592434 (1997-01-01), Iwamoto et al.
patent: 5603009 (1997-02-01), Konishi et al.
"Advances in DRAM Interfaces", by Kumanoya et al., IEEE Micro, vol. 15, No. 6, Dec. 1, 1995, pp. 30-36.
"Fast DRAMs Can Be Swapped for SRAM Caches", by Bursky, Electronic Design, vol. 41, No. 15, Jul. 22, 1993, pp. 55-56, 60, 62, 64, 66, and 70.
"A Multimedia 32B RISC Microprocessor with 16Mb DRAM", by Shimizu et al., IEEE International Solid State Circuits Conference, vol. 39, Feb. 1, 1996, pp. 216-217, 448.
"A 180MHz Multiple-Registered DRAM for Low-Cost 2MB/Chip Secondary Cache", by Iwamoto et al., Proceedings of the Custom Integrated Circuits Conference, May 1, 1998, pp. 591-594.
"A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU", by Dosaka et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1, 1996, pp. 537-544.

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