Memory input signal buffer circuit

Details Memory input signal buffer circuit Memory input signal buffer circuit

1976-03-22

1977-07-26

Heyman, John S.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307355, 307270, 307279, 307DIG1, 307DIG3, 307DIG4, H03K 520, H03K 518, H03K 3286, H03K 3353

Patent

active

040385671

ABSTRACT:
A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.

REFERENCES:
patent: 3639787 (1972-02-01), Lee
patent: 3760381 (1973-09-01), Yao
patent: 3835457 (1974-09-01), Yu
patent: 3891977 (1975-06-01), Amelio et al.
patent: 3892984 (1975-07-01), Stein
patent: 3949381 (1976-04-01), Dennard et al.
patent: 3959781 (1976-05-01), Mehta et al.
Jacobson et al., "Memory Bit Driver"; IBM Tech. Discl. Bull.; vol. 15, No. 6, pp. 1734-1735; 11/1972.
Furman et al., "Sense Latch Circuit for Memory Cells", IBM Tech. Disc. Bull.; vol. 16, No. 9; pp. 2792-2793; 2/1974.

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