Excavating
Patent
1979-04-27
1982-06-15
Atkinson, Charles E.
Excavating
371 40, G06F 1110
Patent
active
043354580
ABSTRACT:
A memory in which each word location for a user word not only contains the bit locations for the actual data but also one parity bit for the parity over the entire word location and one correction bit. A fixed number of word locations are grouped to form a memory location for the storage of a memory word. When a word location is read by a data user, the parity bit indicates whether the word location contains none or one bit error. If the user word contains an error, the other word locations of the same memory location and also the associated correction bits are read to correct one arbitrary bit error in the memory word. In given cases, a plurality of bit errors can be corrected if they are situated in bit positions of the same rank within the word locations for the user words. The chance that a multiple error has exactly this configuration can be enhanced by a suitable arrangement of the bit locations in a memory. Thus, a limited amount of redundancy suffices in many cases. Memory words in different memory banks may have correction bits in common.
REFERENCES:
patent: 3851306 (1974-11-01), Patel
patent: 3893070 (1975-07-01), Bossen et al.
patent: 3893071 (1975-07-01), Bossen et al.
patent: 4072853 (1978-02-01), Barlow et al.
patent: 4077565 (1978-03-01), Nibby, Jr. et al.
patent: 4175692 (1979-11-01), Watanabe
Atkinson Charles E.
Cannon, Jr. James J.
U.S. Philips Corporation
LandOfFree
Memory incorporating error detection and correction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory incorporating error detection and correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory incorporating error detection and correction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1921996