Memory including deep power down mode

Details Memory including deep power down mode Memory including deep power down mode

2006-11-13

2009-08-18

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S228000, C365S233100

Reexamination Certificate

active

07577053

ABSTRACT:
A memory includes an input pad for receiving an input signal and a first circuit. The first circuit is configured to receive a first signal in response to the input signal and receive a second signal and provide a third signal in response to at least one of the first signal and the second signal indicating a request to enter a deep power down mode. The memory includes a second circuit configured to provide a fourth signal indicating an entry to the deep power down mode in response to the third signal.

REFERENCES:
patent: 6016066 (2000-01-01), Ilkbahar
patent: 6477079 (2002-11-01), Kaneko et al.
patent: 6744687 (2004-06-01), Koo et al.
patent: 7154806 (2006-12-01), Kang
patent: 7330067 (2008-02-01), Terayama
patent: 2005/0122820 (2005-06-01), Choi et al.
patent: 2005/0201178 (2005-09-01), Ho et al.
patent: 2005/0243631 (2005-11-01), Akiba et al.

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