Memory in a data processing system having improved performance a

Details Memory in a data processing system having improved performance a Memory in a data processing system having improved performance a

1998-05-21

2000-05-02

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 63, G11C 800

Patent

active

060580658

ABSTRACT:
A memory array is modified by segmenting the total length of a bitline into smaller bitline sections referred to as local bitlines. Included is an additional bitline into the array for every bitline that has been segmented. This new bitline is referred to as the global bitline. After segmentation, the array appears as several smaller sub-arrays; each sub-array has fewer cells per segmentation (local bitline) than the sum total of cells along the more traditional non-segmented bitline approach. These smaller sub-arrays (local bitline segmentations) are independent of one another and only one sub-array can be accessed per memory request (read/write). The reduced length and cell count per local bitline within each sub-array substantially reduces the total bitline capacitance (e.g., diffusion capacitance) discharged by a single memory cell during a read operation. Reducing bitline capacitance results in faster signal development and restore time on the bitline; thus, several smaller sub-arrays can be cycled much faster than a single large array.

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IBM Technical Disclosure Bulletin, vol., 30, No. 5, Oct. 1987, pp. 378-379.

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